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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
PIN CONFIGURATION (TOP VIEW)
DESCRIPTION
The MH1M365CXJ/CNXJ is 1048576-word x 36-bits dynamic RAM. This consists of two industry standard 1M x 16 dynamic RAMs in SOJ and one industry 1M x 4 dyanmic RAMs in SOJ. The mounting of SOJ on a single in-line package provides any application where high densities and large quantities of memory are required. This is a socket-type memory module,suitable for easy interchange or addition of modules.
[Single side]
1.Vss 2.DQ0 3.DQ16 4.DQ1 5.DQ17 6.DQ2
37.MP1 38.MP3 39.Vss 40.CAS0 41.CAS2 42.CAS3 43.CAS1 44.RAS0 45.NC 46.NC 47.W 48.NC 49.DQ8 50.DQ24 51.DQ9 52.DQ25 53.DQ10 54.DQ26 55.DQ11
FEATURES
Type name MH1M365CXJ/CNXJ-5 MH1M365CXJ/CNXJ-6 MH1M365CXJ/CNXJ-7 RAS CAS access access time time (max.ns) (max.ns) Address Cycle Power access dissipatime time tion (max.ns) (min.ns) (typ.mW)
7.DQ18 8.DQ3 11.NC 10.Vcc 11.NC 12.A0 13.A1 14.A2 15.A3
50 60 70
13 15 20
25 30 35
90 110 130
2120 1750 1520
72pin single in-line package Single 5.0V 10% supply Low stand-by power dissipation 16.5mW (Max) Low operating power dissipation MH1M365CXJ/CNXJ- 5 MH1M365CXJ/CNXJ- 6 MH1M365CXJ/CNXJ- 7
16.A4 17.A5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
CMOS lnput level 2.67W (Max) 2.20W (Max) 1.90W (Max)
18.A6 19.NC 20.DQ4 21.DQ20 22.DQ5
Hyper-page mode , RAS-only refresh , CAS before RAS refresh, Hidden refresh capabilities All inputs and output directly TTL compatible 1024 refresh cycles every 16.4ms (A0 ~ A9) MH1M365CXJ MH1M365CNXJ Gold plating Nickel+solder plating
23.DQ21 24.DQ6 25.DQ22 26.DQ7 27.DQ23 28.A7 29.NC
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
30.Vcc 31.A8 32.A9 33.NC 34.RAS2 35.MP2 36.MP0
56.DQ27 37 38 57.DQ12 39 40 41 58.DQ28 42 43 59.Vcc 44 45 60.DQ29 46 47 61.DQ13 48 49 62.DQ30 50 51 63.DQ14 52 53 54 64.DQ31 55 56 65.DQ15 57 58 66.NC 59 60 67.PD1 61 62 68.PD2 63 64 69.PD3 65 66 70.PD4 67 68 69 71.NC 70 71 72.Vss 72
Outline 72N9K-C PD1 PD2 PD3 PD4 -5 Vss Vss Vss Vss -6 Vss Vss NC NC -7 Vss Vss Vss NC
NC: NO CONNECTION
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM FUNCTION
in addition to normal read, write, a number of other functions, e.g., hyper page mode, RAS only refresh, The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs Operation RAS Read Early write RAS-only refresh Hidden refresh CAS before RAS refresh Standby ACT ACT ACT ACT ACT NAC CAS ACT ACT NAC ACT ACT DNC W NAC ACT DNC NAC DNC DNC Row address APD APD APD APD DNC DNC Column address APD APD DNC DNC DNC DNC Input/Output Input OPN VLD DNC OPN DNC DNC Output VLD OPN OPN VLD OPN OPN
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open
BLOCK DIAGRAM
DQ1 DQ3 DQ5 DQ7 DQ9 DQ11 DQ13 DQ15 MP0 DQ0 DQ2 DQ4 DQ6 DQ8 DQ10 DQ12 DQ14 2 4 6 8 20 22 24 26 49 51 53 55 57 61 63 65 36
MP1 37
MP2 35
MP3 38
DQ17 DQ19 DQ21 DQ23 DQ25 DQ27 DQ29 DQ31 DQ16 DQ18 DQ20 DQ22 DQ24 DQ26 DQ28 DQ30 3 5 7 9 21 23 25 27 50 52 54 56 58 60 62 64
LDATA
UDATA 0 1 2 3
LDATA
UDATA
M5M418165CJ
LCAS UCAS
M5M44505CJ
0 1 2 3
M5M418165CJ
LCAS UCAS
44 RAS0
40 CAS0
43 CAS1
12 13 14 15 16 17 18 28 31 32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
34 RAS2
41 CAS2
42 CAS3
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI V0 I0 Pd Topr Tstg Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Ta=25 C With respect to Vss Parameter Conditions Ratings -1 ~ 7 -1 ~ 7 -1 ~ 7 50 3000 0 ~ 70 -40 ~ 125 Unit V V V mA mW C C
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc Vss VIH VIL Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Parameter
(Ta=0 ~ 70 C, unless otherwise noted) (Note 1) Limits Unit V V V V
Min 4.5 0 2.4 -1
Nom 5.0 0
Max 5.5 0 6.0 0.8
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol VOH VOL IOZ II Parameter High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from Vcc operating (Note 3,4,5) ICC2
(Ta=0 ~ 70C, Vcc=5.0V 10%, Vss=0V, unless otherwise noted) (Note 2) Test conditions IOH=-5.0mA IOL=4.2mA Q floating 0V VOUT 5.5V 0V VIN 6 V, Other inputs pins=0V Limits Min 2.4 0 -10 -30 Typ Max Vcc 0.4 10 30 485 400 345 RAS= CAS =VIH, output open RAS= CAS Vcc - 0.2 V RAS cycling, CAS= VIH tRC=min. output open 6 3 485 400 345 455 360 305 465 385 335 mA mA mA mA mA Unit V V A A
MH1M365C MH1M365C MH1M365C
-5 -6 -7
ICC1 (AV)
RAS, CAS cycling tRC=tWC=min. output open
Supply current from Vcc , stand-by (Note 6) Average supply current from Vcc refreshing (Note 3,5) Average supply current from Vcc Hyper-Page-Mode (Note 3,4,5) Average supply current from Vcc CAS before RAS refresh mode (Note 3) MH1M365C MH1M365C MH1M365C MH1M365C MH1M365C MH1M365C MH1M365C MH1M365C MH1M365C -5 -6 -7 -5 -6 -7 -5 -6 -7
ICC3 (AV)
ICC4(AV)
RAS=VIL, CAS cycling tPC=min. output open
ICC6(AV)
CAS before RAS refresh cycling tRC=min. output open
Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc3 (AV) and Icc4 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be changed once or less while RAS=VIL and CAS=VIH .
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
CAPACITANCE (Ta=0 ~ 70 C, Vcc=5.0V 10%, Vss=0V, unless
Symbol CI (A) CI (W) CI (RAS) CI (CAS) CI / O Parameter Input capacitance,address inputs Input capacitance, write control input Input capacitance, RAS input Input capacitance, CAS input Input/Output capacitance, data ports VI=Vss
otherwise noted) Test conditions Limits Min Typ Max 30 36 36 29 22 Unit pF pF pF pF pF
f=1MHZ Vi=25mVrms
SWITCHING CHARACTERISTICS
Symbol
(Ta=0 ~ 70 C, Vcc = 5V 10%, Vss=0V, unless otherwise noted , see notes 6,14,15) Limits
Parameter Access time from CAS Access time from RAS Column address access time Access time from CAS precharge Output hold time from CAS (Note 13) Output hold time from RAS Output low impedance time from CAS low (Note 7) (Note 12) Output disable time after WE high Output disable time after CAS high Output disable time after RAS high (Note 12,13) (Note 12,13) (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11)
MH1M365C -5 Min Max 13 50 25 30 5 5 5 13 13 13
MH1M365C -6 Min Max 15 60 30 35 5 5 5 15 15 15
MH1M365C -7 Min Max 20 70 35 40 5 5 5 20 20 20
Unit ns ns ns ns ns ns ns ns ns ns
tCAC tRAC tAA tCPA tOHC tOHR tCLZ tWEZ tOFF tREZ
Note 6: An initial pause of 500s is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS clock such as RAS-Only refresh). Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 16.4 ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-5mA) / VOL=0.4V(IOL=-4.2mA) load 100pF. The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL). 8: Assumes that tRCD tRCD(max) and tASC tASC(max) and tCP t CP(max). 9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD tRAD(max) and tASC tASC(max). 11: Assumes that tCP tCP(max) and tASC tASC(max). 12: tWEZ(max) ,tOFF(max) and tREZ(max)defines the time at which the output achieves the high impedance state ( and is not reference to VOH(min) or VOL(max). 13: Output is disabled after both RAS and CAS go to high. IOUT I 10 A I)
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM TIMING REQUIREMENTS (For Read, Write, Refresh, and Hyper-Page Mode Cycles)
(Ta=0 ~ 70C, Vcc = 5V 10%, Vss=0V, unless otherwise noted See notes 14,15) Limits MH1M365C -6 Min 40 37 20 5 0 10 25 10 15 0 0 10 10 0 15 15 50 1 50 13 30 45 Max 16.4 50 20 5 0 10 15 0 0 10 10 0 20 20 1 50 13 35 50
Symbol
Parameter Refresh cycle time RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width
Column address delay time from RAS low
MH1M365C -5 Min Max 16.4 30 (Note16) 18 5 0 8 (Note17) (Note18) 13 0 0 8 8 (Note19) (Note20) (Note20) (Note21) 0 13 13 1
MH1M365C -7 Min Max 16.4
Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tRDD tCDD tT
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low Column address hold time after CAS low Delay time, data to CAS low Delay time, RAS high to data Delay time, CAS high to data Transition time
Note 14: The timing requirements are assumed tT =3ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. 17: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. 19: tDZC must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol Parameter Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read Setup time before CAS low Read hold time after CAS high Read hold time after RAS high Column address to RAS hold time Column address to CAS hold time (Note 22) (Note 22) MH1M365C Min 90 50 8 40 13 0 0 10 25 13 10000 10000 -5 Limits MH1M365C Min 110 60 10 48 15 0 0 10 30 18 10000 10000 -6 MH1M365C Min 130 70 13 55 20 0 0 10 35 23 10000 10000 -7 Unit ns ns ns ns ns ns ns ns ns ns
Max
Max
Max
tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Write Cycle (Early Write)
MH1M365C Min -5 Limits MH1M365C Min 110 10000 10000 60 10 48 15 0 10 10 0 10 10000 10000 -6 MH1M365C Min 130 70 13 55 20 0 13 13 0 13 -7
Symbol
Parameter Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low Write hold time after CAS low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low
Unit ns
Max
Max
Max 10000 10000 ns ns ns ns ns ns ns ns ns
tWC tRAS tCAS tCSH tRSH tWCS tWCH tWP tDS tDH
90 50 8 40 13 0 8 8 0 8
Hyper page Mode Cycle (Read, Early Write, Hi-Z control by W)
(Note 25)
Symbol
Parameter Hyper page mode read/write cycle time Output hold time from CAS low RAS low pulse width for read write cycle CAS high pulse width RAS hold time after CAS precharge Hold time to maintain the data Hi-Z until CAS access W Pulse Width (Hi-Z control) (Note24) (Note25)
MH1M365C Min
-5
Limits MH1M365C Min 25 5 77 10 35 7 7
-6
MH1M365C Min 30 5
-7
Unit ns
Max
Max
Max ns ns ns ns ns ns
7 Note 23: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 24: tRAS(min) is specified as two cycles of CAS input are performed. 25: tCP(max) is specified as a reference point only.
tHPC tDOH tRAS tCP tCPRH tCHOL tWPE
20 5 65 8 30 7 7 100000 13
100000 16
92 13 40 7
100000 16
CAS before RAS Refresh Cycle
Symbol tCSR tCHR Parameter
(Note 26) Limits MH1M365C Min 5 10
MH1M365C Min 5 10
-5
-6
MH1M365C Min 5 15
-7
Unit ns ns
Max
Max
Max
CAS setup time before RAS low CAS hold time after RAS low
Note 26: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
Timing Diagrams Read Cycle
(Note 27)
tRC tRAS VIH VIL tCSH tCRP VIH CAS VIL tRAD tASR VIH A0~A9 VIL tRAH tASC tCAH
ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tCRP
tRAL tCAL
tASR
ROW ADDRESS
COLUMN ADDRESS
tRCS VIH VIL tDZC VIH
DQ(INPUTS)
tRRH tRCH
W
tCDD tRDD Hi-Z
VIL tCAC tAA tCLZ VOH
DQ(OUTPUTS)
tREZ tOHR
DATA VALID
tWEZ tOFF tOHC
Hi-Z VOL tRAC
Hi-Z
Note 27
Indicates the don't care input. VIH(min) VIN VIH(max) or VIL(min) VIN VIL(max) Indicates the invalid output.
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
Early Write Cycle
tWC tRAS VIH VIL tCSH tCRP VIH CAS VIL tASR VIH A0~A9 VIL tASR tRAH tASC tCAH
COLUMN ADDRESS ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tCRP
ROW ADDRESS
tWCS W VIH VIL tDS VIH
DQ(INPUTS)
tWCH
tDH
DATA VALID
VIL
VOH
DQ(OUTPUTS)
Hi-Z VOL
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tRAD tASR VIH A0~A9 VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRCS tCAL VIH W VIL tDZC tCAL tCAL
tRRH tRCH
tWEZ tRDD tCDD tCAC tAA tCLZ Hi-Z tCAC tAA tDOH
DATA VALID-1 DATA VALID-2
VIH
DQ(INPUTS)
VIL
tCAC tAA tDOH
tREZ tOHR tOFF tOHC
DATA VALID-3
VOH
DQ(OUTPUTS)
Hi-Z tRAC
VOL
tCPA
tCPA
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
Hyper Page Mode Early Write Cycle
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tCAL tASR VIH A0~A9 VIL tRAH tASC tCAH tASC tCAH tASC tCAL tCAH tRCD tCAS tCP tHPC tCAS tRSH tCP tCAS
tRP
tCRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tWCS VIH W VIL tDS
tWCH
tWCS
tWCH
tWCS
tWCH
tDH
tDS
tDH
tDS
tDH
VIH
DQ(INPUTS)
VIL
DATA VALID-1
DATA VALID-2
DATA VALID-3
VOH
DQ(OUTPUTS)
Hi-Z
VOL
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by W )
tRAS VIH VIL tCSH tCRP VIH CAS VIL tRAD tASR VIH A0~A9 VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
RAS
tCRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRAL tRCS VIH VIL tDZC tWPE tRCH tRCS W
tRRH tRCH
tRDD tCDD tCAC tAA
VIH
DQ(INPUTS)
VIL
tCAC tAA tCLZ
tCAC tAA tDOH
DATA VALID-1
Hi-Z
tWEZ
DATA VALID-2
tCLZ Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
VOH
DQ(OUTPUTS)
Hi-Z tRAC
VOL
tCPA
tCPA
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
RAS-only Refresh Cycle
tRC tRAS VIH RAS VIL tRPC tCRP VIH CAS VIL tASR tRAH tASR tCRP tRP
VIH A0~A9 VIL
ROW ADDRESS
ROW ADDRESS
VIH W VIL
VIH
DQ(INPUT)
VIL
VOH
DQ(OUTPUT)
Hi-Z
VOL
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MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC tRP VIH RAS VIL tRPC tCSR VIH CAS VIL tCPN tCHR tRAS tRAS
tRC tRP
tRPC
tCSR
tCHR
tRPC
tCRP
tASR VIH A0~A9 VIL tRRH tRCH VIH W VIL tRCS
ROW ADDRESS COLUMN ADDRESS
VIH
DQ(INPOUT)
VIL
VOH
DQ(OUTPUT)
tREZ tOHR tOFF tOHC Hi-Z
VOL
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 28)
tRC tRAS VIH RAS VIL tCRP VIH CAS VIL tRAD tASR VIH A0~A9 VIL tRAH
ROW ADDRESS
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
tASC
tCAH
COLUMN ADDRESS
tASR
ROW ADDRESS
tRCS
tRAL
tRRH tRCH
VIH W VIL tDZC tCDD tRDD VIH
DQ(INOUT)
Hi-Z VIL tCAC tAA tCLZ Hi-Z VOL tRAC
DATA VALID
tREZ tOHR tOFF tOHC Hi-Z
VOH
DQ(OUTPUT)
Note 28: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
72pin DRAM Module Outline
107.95 5.08MAX 3.38 101.19
20.2 10.16
1
72
R1.57
5.96MIN.
6.35
2.03
R1.57
1.27
1.27
6.35
35x1.27=44.45
6.35
35x1.27=44.45
2-o3.18
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